Can events be passed as an input parameter to module

SystemVerilog
5

In reply to dave_59:
I am also getting same error " An event is not a legal rvalue in this context [9.7.3(IEEE)]." for below piece of code.

module part (IN, RSEL, OUT);
inout IN;
inout RSEL;
inout OUT;

event trig;
Freq measure_Freq (RSEL, trig);//Instantiation
endmodule 

module Freq (input logic signal, event trigger);
	time t0, t1, timeperiod;
	real freq;//time wont work
	always @(trigger)
	 begin
   	  @ (posedge signal) t0 = $realtime;
    	  @ (posedge signal) t1 = $realtime;
       		timeperiod = t1-t0;
    		freq = 1/timeperiod;
    	  $display("freqams = %t", freq);
  	end
endmodule

@dave_59 / anyone, can you please help me with this error. Thanks!