Can anyone explain me what a blueprint is?

SystemVerilog
5

In reply to chrisspear:

Cannot understand why Bad_Generator code is not working…

class Test;
  Bad_Generator gen;
  //Generator gen;
  
  AXI_TR_ADDR tx_addr;
    
  function new();
    
    gen = new();
    gen.tx = tx_addr; /// <- here we overried the original AXI_TR with AXI_TR_ADDR
                      // So AXI_TR_ADDR constraint should work FIXED_ADDR_100. But NO
                      // WHY??
  endfunction
 
  task run();
    gen.run();
  endtask
enclass