In reply to Suhas BV:
A blueprint is defined as a design plan or other technical drawing
In his book SystemVerilog for Verification (a good book BTW), Chris Spear was referring to SystemVerilog classes being blueprints, or templates, that can be used to build many objects. Blueprints are thus templates that contain objects. Blueprints are typically transformed into actual and usable design plans by either having them approved as is, or modified to needs and then approved.
- Crhis was using a house plan as an example to explain OOP. House blueprint can be momodified (e.g., a different kind of refrigerator, different flooring, roofing material, etc…) and then approved by the city for a building permit, i.e., to be used.
- In OOP, a class is like a blueprint of an entity that contains variables, functions, and tasks. To be used, a class can be extended, if needed, and then instantiated, and that handle uniquely identifies your desired class object. Note that the building permit that uses the updated house blueprint is also a handle that uniquely identifies your house.
- In my SVA Handbook 4th Edition I present blueprints for the design of a requirement apec and a verification spec.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115