So I have bunch of registers which are volatile and will change internally.
But if I can totally understand and predict their behaviors, can I just implement them as quirky registers?
A quirky register behavior is not part of the standard UVM library, so you have to make code that mimics it.
A volatile register’s value can be changed by the hardware at any time. You can model this as a quirky register by duplicating the hardware’s behavior and timing. This could become complex for something like a status register that goes IDLE, STARTING, RUNNING, ENDING, DONE, and many branches. You might end up duplicating the RTL, which defeats the idea of the testbench independently predicting the hardware results.
Let us know how it goes!
I don’t want to duplicate the RTL, what I want to do is to create an abstract reference model which is simpler than the RTL to predict it.
But do you think that a reference model will still end up duplicating the RTL?
You should never look into the direction duplicating the RTL.The intention is to use as a reference model a so-called high-level model, like a TL model or a C-model. This requires a different thinking and talking to different people like system designers etc.
If we do a TL model, does this model require cycle-accurate?
No, Transaction-level Modelling (TLM) does not know anything about clock cycles. It is based on packets.
We are differentiating between 3 different modes:
(1) normal, i.e. 1 input packet generates 1 output packet. After receiving the outputs we can provide the next input packet.
(2) pipelined, i.e. we have more than 1 command on the input side any expect the outputs in the same order as the commands were executed.
(39) out-of-order, i.e. like pipelined, but we expect the outputs in a different order as the commands were executed.
Thanks.
But it sounds getting away from my original question.
It sounds like TLM is just for communicating with the dut.
My goal is to model and verify the volatile registers in my dut which is a slave device.
I want to check whether the read value of the volatile registers is correct or not.
I don’t see how TLM can help me to achieve that.
Of course not. Checking the register content is only a small subtask of verification. I was assuming you will do more.
Checking the register content can be done by using the UVM register layer. This is a mirror of your DUT registers. Evaluating volatile registers requires always an update call. Then you can read your registers from the mirror.