Can a register model be connected to 2 different adapters/agents ? One agent for write and another for read?

UVM
,
6

In reply to VerifEx:

If you have 2 seperate Interfaces and want to perfrom RAL operations with both,
then all you need to have 

1. A adaptor for each interface 

2. A register_map for each interface  
	uvm_reg_map map1, map2; 

   //Create both the maps
   map1 = create_map(.name("map1"), .base_addr('h0), .n_bytes(4), .endian(UVM_LITTLE_ENDIAN));
   map2 = create_map(.name("map2"), .base_addr('h0), .n_bytes(4), .endian(UVM_LITTLE_ENDIAN));

   //Add the register/s to both the maps
   map1.add_reg( .rg(REG1), .offset(8'h0), .rights("RW"));
   map2.add_reg( .rg(REG1), .offset(8'h0), .rights("RW"));
	
3. Provide connetion of each reg_map to its own adapter & sequencer
    h_env.h_reg_block.map1.set_sequencer(.sequencer(h_agt_1.h_seqr),.adapter(h_agt_1.h_adapter));
    h_env.h_reg_block.map2.set_sequencer(.sequencer(h_agt_2.h_seqr),.adapter(h_agt_2.h_adapter));
	
    //also you need to set predictor's map,adapter,ap 
	
4. Specify the needed map while performaing write/read 

   h_env.h_reg_block.REG1.write( op_status, 'hAB,  .path(UVM_FRONTDOOR), .map(map1), .parent(null));   
   h_env.h_reg_block.REG1.read ( op_status, rd_data,  .path(UVM_FRONTDOOR), .map(map2), .parent(null));