In reply to ben@SystemVerilog.us:
OK, when I am wet, I AM WET!
My apologies for making a mistake. Here are my conclusions after
a discussion with a colleague:
1800 pg. 591
Bit vector system functions (20.9) **
$countbits $countones $onehot $onehot0 $isunknown**
Those are functions evaluated when they are seen, there is no scheduling
in the Reactive region as I incorrectly surmised.
Also, with
x_prop_on_d_assert2 : assert property (@(a) !$isunknown( sample() ))
passfn=passfn+1; else
failfn=failfn+1;
the sample() evaluates in the Observed region where “a” is now ==1
That explains the difference between
(@(a) !$isunknown( sample() )) // a==value in Observed
(@(a) !$isunknown( a )) // a==sampled value
Ben