Calling a function within assert property

In reply to ben@SystemVerilog.us:

Hi Ben ,
I get your point but Section 16.11 of the LRM also tells us that subroutine calls are always attached to a sequence expression.
However we are able to call system function $isunknown without attaching it to a sequence_expr .Eg : ( 1 , $isunknown( sig ) )
So according to definition in Section 16.11 , $isunknown shouldn’t be considered a subroutine , right ?
Whereas system task $display can’t be called without attaching it to a sequence expression , hence $display would be considered a subroutine.