Bypassing register access error from reg model or reg map

UVM
1

Hello

Is there a way to bypass a register access error from reg map or reg model into monitor or scoreboard?

Please answer.

Thank you

2

In reply to jaswanth_b:

Hi Jaswanth,

Can you please provide your error message? and explain at what is your code by which you got the error?

3

In reply to mitesh.patel:

REG is read-only. Cannot call write() method
error is like if we write into read only register or vice versa.

could you please tell me how to send this error to monitor or scoreboard.

4

In reply to jaswanth_b:

As per uvm-1.1, uvm_reg or UVM RAL classes doesn’t shout any error if you perform illegal operation. i mean if you perform write operation on read only register with front door path, then RAL will start the sequence on assigned sequencer, it will not check for register access.

So, Can you elaborate the question? point the exact problem you’re facing along with code(if possible)

Regards,
Mitesh Patel

5

In reply to mitesh.patel:

I am doing a write to some register like

reg_i.write(.status(status),.value(32’h0000_00FF),.path(UVM_FRONTDOOR),.parent(this));

I am using reg adapter for this write to a read only register.

6

In reply to jaswanth_b:

RAL should not shout any error if you performed mentioned operation on read only register.
It will convert the register item to bus item based on your register adapter implementation and start the sequence on assigned sequencer.
Actually, design should have that logic to no write on read only register. RAL will just drive on sequencer.

7

In reply to mitesh.patel:
This is not true. What you say means you would not need any access functionality in the RAL.
When you are using the FRONTDOOR access you cannot write RO registers. This will be reported. But you can write them using the BACKDOOR.

8

In reply to chr_sue:

So, please tell me how to bypass this error

9

In reply to jaswanth_b:

Instead of the write command use ‘poke’. This is a backdoor command.

10

In reply to chr_sue:

As per the uvm-1.1 implementation, i think it will start the sequence of assigned sequencer if path is front door. i agree that prediction will be affect if we perform write operation of read only register.
Can you please check and correct me if above understanding is not correct?

Thanks and Regards,
Mitesh Patel

11

In reply to chr_sue:

This is same as doing write() with backdoor path right

12

In reply to mitesh.patel:

In reply to chr_sue:
As per the uvm-1.1 implementation, i think it will start the sequence of assigned sequencer if path is front door. i agree that prediction will be affect if we perform write operation of read only register.
Can you please check and correct me if above understanding is not correct?
Thanks and Regards,
Mitesh Patel

I was just running an example. I observed the following behavior:
If you are trying to execute a frontddor WRITE on a RO, it is simply not doing this command, without any warning or complaint.

13

In reply to chr_sue:

Agree to that, RAL will no shout any error while doing front door write on RO register. it will just start the sequence on assigned sequencer. design should have that control to ignore write operation on RO register.

14

In reply to mitesh.patel:

This is not true, because this might be what you want to verify. The register sequence is simply neglecting this command.