Bypassing register access error from reg model or reg map

In reply to mitesh.patel:

In reply to chr_sue:
As per the uvm-1.1 implementation, i think it will start the sequence of assigned sequencer if path is front door. i agree that prediction will be affect if we perform write operation of read only register.
Can you please check and correct me if above understanding is not correct?
Thanks and Regards,
Mitesh Patel

I was just running an example. I observed the following behavior:
If you are trying to execute a frontddor WRITE on a RO, it is simply not doing this command, without any warning or complaint.