Boundaries of $past(d) and current value of d for verifying D flip flop

SystemVerilog
1

Could someone demarcate the boundaries of $past(d) and current value of d so that assertion passes visually.
Additionally, where would $sampled(d) be in the figure?

Imgur

2

you can use

(##1; q === $past(d))

in a property. This helps avoid the false trigger at first edge

1 Like
3

@ssureshgverifier Thanks. The problem is still around the boundaries of $past(). If $past() refers to the shaded orange region in the waveform, the assertion should fail but the assertion passes!

4

$past does not represent entire orange region. it gives value sampled in the ‘preponed event region’ during last clk edge. $sampled gives the value sampled at current timestep, again in the preponed region.
above waveform you gave does not show delta cycles to mark SV event region.