Blocking, delayed assignment vs Non-blocking, delayed assignment on a buffer

SystemVerilog
2

*In reply to hsam:*For simulation, it helps to unroll these procedural looping statements.

initial begin
        @(in)
        output <= #5 in;
        @(in)
        output <= #5 in;
        @(in)
        output <= #5 in;
        ...

Using non-blocking assignments, there is no delay between the successive
@(in) constructs, so every change on
in gets caught. The change to
out gets scheduled for 5 time units later for every change of
in. That is the definition of transport delay.

initial begin
        @(in)
        output = #5 in;
        @(in)
        output = #5 in;
        @(in)
        output = #5 in;
        ...

Using blocking assignments, there is a 5 time unit delay between the successive
@(in) constructs, so every change on
in that happens during that delay is lost.
in cannot change faster the the propagation delay to
out. That is the definition of inertial delay.