Bitwise toggle coverage for a bitvector

SystemVerilog
6

In reply to dave_59:

I am trying to construct an array of covergroups in order to sample slices of a parameterized vector as follows:

module checker {
  clk,
  reset, 
  sig
}
parameter WIDTH = 32;
input clk;
input reset;
input [WIDTH-1:0] sig;

// Declare generic covergroup
covergroup CG (ref reg _cp) @ (posedge clk);
  option.per_instance = 1;
  CP: coverpoint _cp;
endgroup 

//Instantiate covergroup
CG cg[32];
for (int i=0; i < WIDTH; i=i+1) begin
  cg[i] = new(sig[i]);
end
endmodule

This line:

CG cg[32]

Is causing the following compiler error: Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.

I guess I need to declare the covergroup outside the module, but I’m not sure what that would look like. Can anyone provide an example of what that looks like in my case?

1 Like