Bitwise toggle coverage for a bitvector

SystemVerilog
16

In reply to dave_59:

Hello Dave, thanks it works well!
because the covergroups declaration is outside the class, i can use parameter to determine the width:

   covergroup mask (input bit [MASK_WIDTH-1:0] position ,ref bit [MASK_WIDTH-1:0] vector);
            mask_cp : coverpoint (position & vector) !=0;
            option.per_instance = 1;
            //option.comment = "";
   endgroup

but if i would like to make it be more flexible, i mean the width will get different value each time, so then a constant parameter is not good for me.
i thought to do it by the factory registration, like that:

`ovm_field_int (m_mask_width, OVM_ALL_ON)

but with this way my covergroups will not recognize it.
how can i declare my covergroups like that?

thanks for your help
Racheli