Bit slicing

SystemVerilog
3

I don’t clearly understand what do you want, but maybe you are looking for something like this:


`uvm_do_with(req, {
  req.dataWord.size == burst_length;
  foreach(req.dataWord[i]) {
    req.dataWord[i] == data[i];
  }
})

Btw, using `uvm_do_with macro is not recommended.
Ref: http://verificationhorizons.verificationacademy.com/volume-7_issue-2/articles/stream/are-ovm-and-uvm-macros-evil-a-cost-benefit-analysis_vh-v7-i2.pdf