Bins converging to empty list

SystemVerilog
1

Hi,

I have defined one coverpoint as below:

pkt_sig:    coverpoint pkt.sig[1:0]  iff(pkt.type inside {A,B,C})
        {
          wildcard bins bit_0[2]    = {2'b?0, 2'b?1};
          wildcard bins bit_1[2]    = {2'b0?, 2'b1?};
          illegal_bins  illegal_sig   = {[2:$]} iff (pkt.type inside {B,C});
        }

For the above code, the bin bit_1[1] is getting converged to empty with a simulator warning as below:

# ** Warning: (vsim-8547) After dropping the illegal, ignore or invalid values, the values list associated with fixed-size array sub bin ‘bit_1[1]’ in Coverpoint ‘pkt_sig’ of Covergroup instance test::cg_inst ’ has converged to empty list. The sub bin will be taken out of coverage calculation.

Can somebody please explain about this warning and what’s wrong in the coverpoint implementation.?

One possible method for the requirement is to create a separate coverpoint for illegal_sig bin.

2

Without the illegal_bins, your coverpoint creates the following 4 bins

bit_0[0] = {0,2} // 2'b?0
bit_0[1] = {1,3} // 2'b?1
bit_1[0] = {0,1} // 2'b0?
bit_1[1] = {2,3} // 2'b1?

Your illegal_bins specification specifies the values {2,3} which 100% overlaps the bin bit_1[1]. So that bin get removed reducing the total number of bins to 3. Realize that bin construction happens irrespective of iff conditions.

I would recommend using an assertion instead.

1 Like
3

Hi Dave,
Have a few questions about your solution
a) According to the LRM do the indexes for bit_0 / bit_1 vary from 0-1 or 1-2 ?
b) How are the 4 possible values using {2’b?0, 2’b?1} distributed for the 2 bins for bit_0 ?
c) When pkt.sig[1:0] == 2’b10 ( assume pkt.type == B/C ) ,
would bins bit_0[0] as well as illegal_sig be hit ?

4

a)

For integral state bins declared as “binname[],” bin names are “binname[value].” For state bins declared as “binname[N],” bin names range from “binname[0]” through “binname[N-1].”

b)
wildcard bins bit_0[2] = {2'b?0, 2'b?1}; is the same as bins bit_0[2] = {2'b00,2'b10, 2'b01,2'b11};
c)

No, bit_0[0] would still have the value 2'b00. 2'b10 is the only value removed from that bin.

5

Thanks Dave
I found the quote from LRM 19.11.3

For state bins declared as “binname[],” bin names are “binname[value]” (as specified in 19.5.1 ) for a set of scalar values. 
Instances sharing the same value have overlapping bins. 
For state bins declared as “binname[N],” bin names range “binname[0]” through
“binname[N-1].”

Regarding b) :: {2’b?0, 2’b?1} is the same as {2’b00,2’b10, 2’b01,2’b11}
[Q] Would the ‘?’ always loop left to right ( incase of multiple ? ) from 0 to 1 ( instead of looping from 1 to 0 ) ?
There could be cases where the way ? loops could possibly affect the values associated with the bins
Eg: When the number of values isn’t an integer multiple of number of bins

6

Note that I am quoting the recently released IEEE 1800-2023 SystemVerilog standard which clarifies that the bin naming applies to integral state bins. So there is always an integer number of bins.

The LRM is not explicit, but I think you can safely assume the looping goes from 0 to 1 in numerical order.