Binding a Checker declared within a module

SystemVerilog
,
1

Consider the code below,

interface some_if;
  
  	logic s1;
  	logic s2;
  	logic s3;
endinterface


module tb;
  
  checker some_checker;

  endchecker : some_checker

  
  some_if if_inst();
  
  bind if_inst some_checker ch();
 
  
endmodule

Although checker declaration is allowed within a module, most of the EDA tools I’ve tried in edaplayground.com fails to elaborate the code above. Some of them passes when bind statement is removed. Is this due to tool flaw or incompliance with the LRM? If so, can someone point me the resources in LRM?

2

I believe that is one of the least supported constructs (unfortunately) in simulators today.

3

Should we avoid using altogether? :))
Have you experienced any project with significant usage of checkers?

4

I think the problem is the combination of bind with a checker defined inside a module. Declaration inside module are not visible outside that module except where hierarchical references are allowed, which is not the case here.

Moving the checker declaration outside the module works on 3 of 4 simulators on EDAPlayground. That other simulator doesn’t even recognize checker as a keyword.

5

I was a big time promoter of this feature during our SVA book writing with @Ajeetha_Kumari_CVC and @ben2 - but was disappointed with simulator support beyond simple uses. I learnt that the “free/rand variable” feature within checker is the key reason why this was added to the language at the first place and that’s mostly for formal tools. I am not sure how many FV tools really support this today - though they all have ways to do “cutpoints” and modeling code without checker.

So, yes I would like to see more and more checker usage - but being pragmatic, tool support is quite behind.

6

From your perspective I’ve tried to reference via tb.some_checker but still giving an error. Moving the checker outside works as expected. Anyways, I will probably skip using checkers.

bind if_inst tb.some_checker ch();
7

Yes, I’ve read your paper about checkers for cache controller as well. That was inspiring, thanks.
I was suprised when I see checker was primarily targeted for formal in LRM.

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