Bind multiple design instances of a block

SystemVerilog
1

I would like to bind a module binder as shown in the code to all the module instances of dut_sub, so that we have different bind instances for all of them.

module dut_sub (
 
	input logic clk,
	input logic [1:0] avalid);
		
endmodule

module dut
	
	(input logic clk_dut,
	input logic [1:0] avalid_dut);

	dut_sub dut_sub_inst[7:0] (.clk(clk_dut), .avalid(avalid_dut));

endmodule

module binder(input [1:0] avalid);
endmodule

module top;

	logic clk_top;
	bit [1:0] avalid_top;
	initial begin 
		clk_top = 0;
		forever #5 clk_top = ~clk_top;
	end 

//	generate
//	for(genvar i = 0; i<8 ; i++) begin 
//	bind dut_sub binder u_binder[i](.avalid(top.u_dut.dut_sub_inst[i].avalid));
//	end
//
//	endgenerate

	bind dut_sub binder u_binder(.avalid(top.u_dut.dut_sub_inst[0].avalid));
	// Using the above code we do see a bind per instance of dut_sub, but all
	// of them will have avalid which is the avalid of instance 0 of dut_sub.
	// something as follow: 
//	top.u_dut.dut_sub_inst[1].u_binder.avalid[1:0].(top.u_dut.dut_sub_inst[1].avalid);
//	top.u_dut.dut_sub_inst[2].u_binder.avalid[1:0].(top.u_dut.dut_sub_inst[2].avalid);
//	top.u_dut.dut_sub_inst[3].u_binder.avalid[1:0].(top.u_dut.dut_sub_inst[3].avalid);
//	top.u_dut.dut_sub_inst[4].u_binder.avalid[1:0].(top.u_dut.dut_sub_inst[4].avalid);

	dut u_dut (.clk_dut(clk_top), .avalid_dut(avalid_top));
	
	initial begin 
		$fsdbDumpvars();
	end 
	initial 
		begin 
		#50 $finish();
		end
endmodule

anyway doing this via bind?

2

The way bind works is the signals are resolved in context. See following code, look at u_2_binder, I believe it does what you wanted.

module dut_sub (
 
	input logic clk,
	input logic [1:0] avalid);
  initial begin
    #10;
    $display ("Signal full name is: %m.avalid val: %b", avalid);
  end
		
endmodule

module dut
	
	(input logic clk_dut,
     input logic [7:0] [1:0] avalid_dut);

	dut_sub dut_sub_inst[7:0] (.clk(clk_dut), .avalid(avalid_dut));

endmodule

module binder(input [1:0] avalid);
  
  initial begin
    #10;
    $display ("Signal full name is: %m.avalid val: %b", avalid);
  end
  
endmodule

module top;

	logic clk_top;
  bit [7:0] [1:0] avalid_top;
	initial begin 
		clk_top = 0;
      avalid_top = $urandom();
      $display ("top: avalid_top: %b", avalid_top);
		forever #5 clk_top = ~clk_top;
	end 

//	generate
//	for(genvar i = 0; i<8 ; i++) begin 
//	bind dut_sub binder u_binder[i](.avalid(top.u_dut.dut_sub_inst[i].avalid));
//	end
//
//	endgenerate

	bind dut_sub binder u_binder(.avalid(top.u_dut.dut_sub_inst[0].avalid));
	bind dut_sub binder u_2_binder(.avalid(avalid));
	// Using the above code we do see a bind per instance of dut_sub, but all
	// of them will have avalid which is the avalid of instance 0 of dut_sub.
	// something as follow: 
//	top.u_dut.dut_sub_inst[1].u_binder.avalid[1:0].(top.u_dut.dut_sub_inst[1].avalid);
//	top.u_dut.dut_sub_inst[2].u_binder.avalid[1:0].(top.u_dut.dut_sub_inst[2].avalid);
//	top.u_dut.dut_sub_inst[3].u_binder.avalid[1:0].(top.u_dut.dut_sub_inst[3].avalid);
//	top.u_dut.dut_sub_inst[4].u_binder.avalid[1:0].(top.u_dut.dut_sub_inst[4].avalid);

	dut u_dut (.clk_dut(clk_top), .avalid_dut(avalid_top));
	
	initial begin 
		$fsdbDumpvars();
	end 
	initial 
		begin 
		#50 $finish();
		end
endmodule