Hi,
1)Yes. For example I have 3 RTL modules that connected one to another.
ModuleA → ModuleB → ModuleC
IF1 IF2
I would like to drive IF1 and IF2 instead of ModuleA and moduleB respectively.
But the way I want to do it is as mentioned. Encapsulate IF1 and IF2 in a virtual IF with a task that controls whether I force a VIP on them or not, send it to the UVM factory, and use the task during the simulation.
2) RTL drivers are moduleA and moduleB in my example.
3) The design is in Verilog and I do verification in SV and UVM.
Thanks.