Bind interface for internal DUT forcing

UVM
3

Hi,

Thanks for the response.

  1. The reason for the ports is that I’m trying to create a generic IF that I could connect RTL internal AXI interfaces in different blocks in my DUT, and force them to an AXI VIP. If I won’t use ports I’ll have to create an individual IF per RTL AXI end point.
  2. No, I’m binding the generic IF I created (vip_axi_wrapper_lbw_if) to my DUT that instantiated in the top_tb. After that I’m passing it through the factory to my agent, which will initiate the internal IF task that force the ports which was binded to the DUT.

I managed to make this work in the EDA playground with a simple example. But since I’m using the set_config_db to pass the virtual IF, I think it might cause this to fail.

Please advise.

Thanks,
Berry