In reply to chr_sue:
@chr_sue, no, my DUT doesn’t have any indication. That’s the tricky part. But i think, i can come up with approximate number of clock cycles(using some parameters). Need to see. DuT generates addresses, wr_en for two different RAMs after an input trigger with some deliberate delays in between.
BTW, if at all there is an acknowledgement, how do we handle? Is it through an uvm_event from monitor to driver? Was just curious to know.
Thank you!
I came across a link related to above topic: