In reply to chr_sue:
Thanks Chris,
I could almost achieve what i wanted. Will keep the above option in my mind.
I have 2 questions, which i came across with this TB:(Please let me know if i need to raise these questions separately in the forum)
- In sequence, I was trying to wait for uvm_event(triggered in driver). But got a loading error for configdb check line. I removed it and added few extra sequences to take care of it. Can’t we use uvm_event in sequence?
class grp_ctrl_sequence extends uvm_sequence#(grp_ctrl_seq_item);
grp_ctrl_seq_item req;
uvm_event DELAY_DONE;
virtual task body;
//got a loading error for below
if(!uvm_config_db#(uvm_event)::get(this, "", "driver_event", DELAY_DONE))
`uvm_fatal("NO_UVM_EVENT",{"uvm event must be set for: ",get_full_name(),".driver_event"});
:
:
// DELAY_DONE.wait_trigger();
:
:
endtask
endclass
- There are multiple instances of below RAM in my design. read_addr input is provided by the TB with clocking block. So it has input skew. I did check the waveform to confirm the same. But the strange thing is, rd_data is available in the same clock(i.e. it behaves as if there is no input skew). Below is the code. Any idea, why does it behave so?
module RAM #(
parameter DATA = 16,
parameter ADDR = 4
) (
input logic clk,
// Write Port
input logic wr,
input logic [ADDR-1:0] wr_addr,
input logic [DATA-1:0] wr_data,
// Read Port
input logic [ADDR-1:0] rd_addr,
output logic [DATA-1:0] rd_data
);
// Shared memory
logic [DATA-1:0] mem [(2**ADDR)-1:0];
initial begin
for (int i = 0; i < 2**ADDR; i++) begin
mem[i] = '0;
end
end
// Write Port
always @(posedge clk)
if(wr)
mem[wr_addr] <= wr_data;
// Read Port
logic [ADDR-1:0] rd_addr_reg;
always @(posedge clk)
rd_addr_reg <= rd_addr;
assign rd_data = mem[rd_addr_reg];
endmodule