Behaviour of if else inside always_comb block

SystemVerilog
1

Hi,

always_comb begin
if() // execute code: x==1
else if() // execute code: x==2
else if() // execute code: x==3
end

I am trying to understand what happens when a certain condition doesn’t fall into any of the ‘if else’ mentioned above and there is no else block?

Thank you

2

if none of the if or else if conditions match and there is no else block, then nothing happens, the block simply does not execute any statements.

3

If a variable gets assigned in some, but not all branches of an always_comb process and that variable is read by another, that process does not represent combinational logic and tools are requested to generate a warning.

1 Like
4

So, if I have a same variable being read and written in the always_comb block, and there is no else condition, I am observing that it latches onto the value of the last if else (in this case, x==3).

I didn’t see any warning from the tool and it came out to be false pass

5

The warning is not mandatory. I think systhesis tools should generate a warning.

6

Yes, synthesis tools generate a warning.