Backdoor acess through user defined maps

UVM
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21

In reply to usnath:

Yes chr_sue is right? Your implementation is so weird.
Two thing I don’t understand:
1.


this.field1.configure.add_hdl_path_slice("abc");

In uvm_reg_field class doesn’t has attribute ‘configure’.


reg1.add_hdl_path("xyz");

In uvm_reg class, we only have add_hdl_path with following prototype:


function void uvm_reg::add_hdl_path(uvm_hdl_path_slice slices[],
                                    string kind = "RTL");

Please follow chr_sue example to implement.

22

In reply to cuonghl:

Hi cuonghl,
You’re correct, the correct implementation is


this.field1.add_hdl_path_slice("abc");

The usage you said,


function void uvm_reg::add_hdl_path(uvm_hdl_path_slice slices[],
                                    string kind = "RTL");

is used within the register implementation, outside the implementation for example inside a register block we can do the same as below


this.reg1.add_hdl_path("xyz");

P.S. Please do not consider the code completely, its just for the concept, the real code is very complex and huge.

23

In reply to usnath:

Hi chr_sue and cuonghl,

The problem was basically due to wrong hdl_path being used in the register level(reg.add_hdl_path). I assumed that the compiler will give a error if hdl path does not exist. Seems like it gives error only when there is a error in hdl slices(because I used to get "hdl path not found " errors). Thank you very much for your suggestions.

24

Hi Sirs,

Sorry for appending my question to this thread, since it is related to above discussions.
I am pretty new in UVM and now I am exploring RAL.

I have few things needed to be clarified/confirmed. Thank you in advance for your kind answers…

  1. add_hdl_path is the path to the register block in my DUT?
    So if I have this DUT hierarchy : DUT->CORE->SUBBLOCK->REGBLOCK
    Then my add_hdl_path usage should be below?

    add_hdl_path(“TBTOP.DUT.CORE.SUBBLOCK.REGBLOCK”, “RTL”);

  2. add_hdl_path_slice points to the actual declared register inside the REGBLOCK?
    reg0.add_hdl_path_slice(“REG0”, 0, 8);

  3. I have an auto-generated REGBLOCK, and there is no actual REG0 signal declared.
    The register fields signals are the ones declared directly. How do I add
    add_hdl_path_slice in this case?

P.S. I am trying the built-in sequence like uvm_reg_hw_reset_seq, and getting below:
RegModel : Register “reg_block.REG1*” value read from DUT (0x0000000000000000) does not match mirrored value (0x0000000000010103
This mismatch occur because my add_hdl_path_slice is not set correctly, right?

Thank you!