Backdoor acess through user defined maps

In reply to chr_sue:
Yeah I have implemented similarly. And about the hdl_path being correct, shouldn’t the program give an error if it is not correct, like “hdl_path not found”. And for the record the write to all registers works like a charm when the top_regmodel is swapped with reg_block in set_hdl_path_root.i.e


class reg1 extends uvm_reg;
  this.field1.configure.add_hdl_path_slice("abc");
  //...;
endclass
 
class reg_block extends uvm_reg_block;
  reg1.add_hdl_path("xyz");
  //...;
endclass
 
//class top_regmodel extends reg_block;
//  uvm_regmap spi_map;
//  //.....;
//ensclass
 
class env extends uvm_env;
  reg_block.set_hdl_path_root("pqr");
  //....;
endclass
 
class cb extends uvm_reg_cb;
  virtual task pre_write(uvm_reg_item rw);
    reg_block.reg1.write(status,value,UVM_BACKDOOR); //write does not happen
  endtask
endclass