Backdoor acess through user defined maps

UVM
, ,
17

In reply to usnath:

Looks a Little bits complicated. The reg_model needs the information about the hdl_path_slice this has to be defined for each register. And you have to define the the hdl_path. This looks like this:

class my_reg_block extends uvm_reg_block;
      `uvm_object_utils(my_reg_block)
.....
     rand my_reg0 reg0;
     rand my_reg1 reg1;
.....
     
     function new(string name = "my_reg_block");
         super.new(name, UVM_NO_COVERAGE);
     endfunction
 
     virtual function void build();
         reg0 = my_reg0::type_id::create("reg0");
         reg0.configure(this);
         reg0.build();
	 reg0.add_hdl_path_slice("mode_reg[0]", 0, 8);
..........
       // the same for all other registers
..........
         // Assign dut to the hdl path
         add_hdl_path(<name of the toplevel mod>.dut", "RTL"); // dut is the RTL. The regs are on the toplevel of the dut.
         lock_model();
      endfunction