Backdoor acess through user defined maps

UVM
, ,
15

In reply to cuonghl:[/i]


class reg1 extends uvm_reg;
  this.field1.configure.add_hdl_path_slice("abc");
  //...;
endclass

class reg_block extends uvm_reg_block;
  reg1.add_hdl_path("xyz");
  //...;
endclass

class top_regmodel extends reg_block;
  uvm_regmap spi_map;
  //.....;
ensclass

class env extends uvm_env;
  top_regmodel.set_hdl_path_root("pqr");
  //....;
endclass

class cb extends uvm_reg_cb;
  virtual task pre_write(uvm_reg_item rw);
    top_regmodel.reg_block.reg1.write(status,value,UVM_BACKDOOR); //write does not happen
  endtask
endclass