Automatic variable

SystemVerilog
2

In reply to yourcheers:

module test;
initial begin
for(int i = 0; i < 5; i++)begin
fork
begin
automatic int l = i;             
$display(i,l);
end
join_none
end
end
endmodule

What are the rules for automatic variable declaration? Why in the above code “l” is not behaving like a automatic variable?

In your example i,l display the same value 5 as execution of all threads happen after all of them forked off by that time i is 5.

Each instance of automatic variable mapped to separate memory location in stack.


        for(int i = 0; i < 5; i++)begin
            automatic int l = i;  // will be executed 5 time and mapped to 5 memory location in stack 
        end

Static variables are mapped to fixed memory location.


        for(int i = 0; i < 5; i++)begin
            //int l = i;  // illegal decalration
            int l;  // will be executed only once, mapped to one fixed memory location
            l = i; 
        end

you should use automatic variable when you want map the each instance of variable to separate memory space.
Note : Variable declared in the class is by default automatic.


module test;
    initial begin
        for(int i = 0; i < 5; i++)begin
            automatic int l = i;  
            fork
                begin           
                    $display(i,l);
                end
            join_none
        end
    end
endmodule

//output:
5  0
5  1
5  2
5  3
5  4