In reply to kernalmode1:
One more point on immediate assertions from my SVA book:
In addition, there are two categories of immediate assertions: simple immediate and deferred immediate (specified with #0 or final after the directive, such as assert #0, assert final).
- An assertion that depends only on variables that are updated in a nonblocking manner need not be deferred. This is because all the values are evaluated in the active region but updated in the NBA region.
- An assertion that depends on combinational logic or that uses external signals the use of a deferred assertion is preferable. Is the simulation supports assert final, then use that structure because the action block subroutine is called in the Postponed region.
Thus, you may want to consider:
always_comb if(!rst_n)
assert final(ptr==0);
Ben Cohen
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- https://verificationacademy.com/news/verification-horizons-march-2018-issue
- http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
- “Using SVA for scoreboarding and TB designs”
http://systemverilog.us/papers/sva4scoreboarding.pdf - “Assertions Instead of FSMs/logic for Scoreboarding and Verification”
https://verificationacademy.com/verification-horizons/october-2013-volume-9-issue-3 - SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
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