Asynchronous Assertions

SystemVerilog
, ,
3

In reply to Satputesb:
You still ar enot clear, sorry. WHere is the observaltion of these 3 signals? and when?
Are you saying you have an input in1 where in1–A1, then in1==A2, then in1==A3?
What triggered the selection? I started a module but quickly gave up.
In asynchronous designs, state transitions occur upon events, like sig1==1 then state=N,
then from state N sig2==1 transtions state to state K, and so on.


module m;
  bit A, B, C, in1;  
  bit[1:0] state; 
//  First input signal A1 asserted then input signal A2 and then input signal A3.
// This is the sequence in which A1 , A2 and A3 are arriving. 
  always_latch begin
     if(state==2'b00 && A ) state==2'b01; 
     if(state==2'b01 && B && !A ) state==2'b10; 
     if(state==2'b10 && C && !A && !B) state==2'b11; 
  end