Asynchronous assertion that checks if two signals are equal

SystemVerilog
1

Hi All,

My current task is to check if two signals are equal asynchronously.
I tried to realize it due to concurrent assertion (as it shown below):

property CON_CHECK_ASYNC(d_in, d_out, rst_n);
    @(d_in or d_out) disable iff(!rst_n)
        d_in == d_out;
endproperty

But it sampled in Preponed Region and so it works incorrect. It compares past values of d_in and d_out.
Then I tried to realize it due to immediate assertion (my code below):

always@(d_in or d_out) begin
    if(rst_n) begin
        CON_CHECK_ASYNC_ASR: assert (d_in == d_out) begin
            uvm_info("ABV", $sformatf("Property CON_CHECK_ASYNC successed"), UVM_HIGH) 
        end else begin
            uvm_error(“ABV”, $sformatf("Error. Property CON_CHECK_ASYNC failed ")) 
        end;
        CON_CHECK_ASYNC_COV: cover (d_in == d_out);
    end
end

But it doesn’t work because always block can’t span two signals in sensetivity list and the assertion could pass and fail at the same time (when both d_in and d_out change at the same time).

Has anyone experienced this? Any suggestions on what to do about it?

Thanks,
Valentyn

2

Use a deferred immediate assertion (Section 16.4 in the 1800-2017 LRM) along with always_comb

always_comb
    if(rst_n) 
        CON_CHECK_ASYNC_ASR: assert #0 (d_in == d_out) 
            uvm_info("ABV", $sformatf("Property CON_CHECK_ASYNC successed"), UVM_HIGH) 
        else
            uvm_error(“ABV”, $sformatf("Error. Property CON_CHECK_ASYNC failed "))

Also, there should be no need for a separate cover directive as tools can include assertions in their coverage calculations.

1 Like
3

Thank you for your solution, Dave!