In reply to ben@SystemVerilog.us:
Difference between within/and/intersect: the change is w.r.t. the matching start and end point, right?
I mean if we use “and” that means valid is 1 at the same clock when $changed(data) is detected and if we use “within” that means valid can be 1 anywhere between two changes in data and with “intersect” both valid and data change detection points should match which means the duration of valid is equal to duration between two changes.
am I getting it right?
the problem however is a bit complex it doesn’t say there is any relation of valid high duration with change in data. The more descriptive problem is there should be one valid per data change and that valid should remain asserted until it sees an ack after which it falls. maybe better to break into two assumes.