Associative array with class handles

SystemVerilog
,
2

In reply to rag123:


module tb;
 
  class A;
    int aa;
 
    function new();
      aa=10;
    endfunction
 
    function void printA();
      $display ("aa value from A sequence = %d",aa);
    endfunction  
 
endclass
 
      class B extends A;
        int bb;
 
        function new();
          bb=20;
        endfunction
 
         function void printB();
           $display ("bb value from B sequence = %d",bb);
         endfunction  
 
       endclass
 
 
           class C extends B;
           int cc;
 
        function new();
          cc=30;
        endfunction
 
         function void printc();
           $display ("cc value from C sequence = %d",cc);
         endfunction
 
           endclass  

    typedef A a;
    a a_lib[string];
 
      A a_seq;
      B b_seq;
      C c_seq;
      string sel;
      A a_h;
 
       initial begin
         a_seq = new();
         b_seq = new();
         c_seq =new();
 
 
         a_lib["a"]=a_seq;
         a_lib["b"]=b_seq;
         a_lib["c"]= c_seq;
         
         if(a_lib.first(sel))
           begin
            a_h= a_lib[sel];
           $display("%p",a_h);
            end
        forever 
          begin 
            if(a_lib.next(sel))
              begin
                 a_h= a_lib[sel];
                 $display("%p",a_h);
              end
             else
                break;
          end
     
       end
  
  endmodule

Hope the above code will help you.

Thanks & Regards,
Shanthi V A
www.maven-silicon.com