Associative array mapping in SystemVerilog

SystemVerilog
2

In reply to random_coder:

You can create an associative array to keep track of the number of times you’ve seen each key.

int keyCount[int];

Then in your code you can increment the keyCount each time use see a key repeated.

if(!keyCount.exitsts(key) 
  keyCount[key] = 0; // first time key has been seen
else
  keyCount[key]++;

We would need to see the code that generates your output to one the bet way of integrating it
Creating an alphabetic sequence of key names is not so simple if you are expecting more than 26 keys. Can you use 0-0, 0-1, etc?