In reply to dave_59:
The differences in simulator output means that they have a different
understanding of Specialization of Value parameterized class .
class BB #( VALUE = 0 ) ;
const static string t_name = get() ;
static function string get() ;
$display("TIME:%0t Specialization of BB#(%0d) found " , $time , VALUE );
return $sformatf("BB#(%0d)",VALUE) ;
endfunction
endclass
parameter int INT = 10 ;
BB #( INT ) b1 ;
parameter bit signed [31:0] BITS_31_0 = 10 ;
BB #( BITS_31_0 ) b2 ;
// b1 and b2 are Same Specialization , but Simulators do interpret both as different
parameter bit [31:0] BIT_31_0 = 10 ;
BB #( BIT_31_0 ) b3 ;
parameter bit signed [0:31] BITS_0_31 = 10 ;
BB #( BITS_0_31 ) b4 ;
This too gives different Output across Simulators
which is an issue for a Value Parameterized class when trying to register in Factory !!
This would be an issue when running same UVM Code across simulators .
As you have mentioned the LRM should use “Matching Type” definition in section 8.25
Is there a Mantis Issue reported for this ?
Is it possible to add this to another-revision-systemverilog