Assigning local variable within 'or' V/S 'and' operator

SystemVerilog
,
2

In reply to Have_A_Doubt:
Consider this other example:




  sequence s4;
    int x;
    ( ((1, x = data) ##3 data==x) // seq1
    and 
    ( ##1 (1, x = data) ##1 data==x) ) // seq2
      ##1 data==x; //  seq3
  endsequence
  ap4:assert property( @(posedge clk) s4); 
  
  t0  x=data_@t0  // from seq1  
  t1  x=data_@t1  // from seq2
  t2  evaluate data==x // from seq2
   Question: which x to use? the x from x=data_@t0  or the x from x=data_@t1
  t3  evaluate data==x  // from seq1
  Question: which x to use? the x from x=data_@t0  or the x from x=data_@t1
  t4  evaluate data==x //  from seq3
  Question: which x to use? the x from x=data_@t0  or the x from x=data_@t1

  Please answer the question as to which do you want and why?  
You can argue the last but you can also argue for the variable contained (or braced) within each respective sequence. When you come out of the AND, then what? Which one to choose? 
That is the delemma! 
  Note that the sequences seq1,seq2 are both triggered concurrently and don't know of each other or their variables. The sequences are "braced" and don't communicate.

  That is the reason why an assignment to both concurrent threads (seq1, seq2) is illegal. 
 If a variable is assigned to only one of the threads, the local variable flows out; it's a rule defined in 1800

One can say: "well, take the last value assigned to the local variable as the value that flows out of the ANDed sequences. That does not work though. For example:


 sequence s4;
    int x;
    ( (a ##1b, x = data) and (d ##1e, x = data+2) ) ##1 (data1 == x); // local variable 'x' assigned in both sequence
  endsequence
  ap4:assert property( @(posedge clk) s4);  
Which x flows out? they are both assigned one cycle after the attempt.

Ben Cohen
Ben@systemverilog.us
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