In reply to ben@SystemVerilog.us:
Ben,
Have 2 further questions:
1)
sequence s4;
int x;
( ((1, x = data) ##3 data==x) // seq1
and
( ##1 (1, x = data) ##1 data==x) ) // seq2
##1 data==x; // seq3
endsequence
ap4:assert property( @(posedge clk) s4);
t0 x=data_@t0 // from seq1
t1 x=data_@t1 // from seq2
t2 evaluate data==x // from seq2
Question1: which x to use? the x from x=data_@t0 or the x from x=data_@t1
t3 evaluate data==x // from seq1
Question2: which x to use? the x from x=data_@t0 or the x from x=data_@t1
t4 evaluate data==x // from seq3
Question3: which x to use? the x from x=data_@t0 or the x from x=data_@t1
Please answer the question as to which do you want and why?
Doesn’t the discrepancy lie with only question3 ?
For Q1: Shouldn’t the ‘x’ from seq1 be used ?
For Q2: Shouldn’t the ‘x’ from seq2 be used ?
For Q3: Should ‘x’ from seq1 or seq2 be used ? Not clear hence the compilation error
- Consider the following ‘or’ operator :
sequence s2;
int x;
( (a ##1 b, x = data1) or ( d ##1 e, x = data2) ) ##1 (data == x + 1);
endsequence
ap2:assert property( @(posedge clk) s2);
Although the code is legal, doesn’t there exist a discrepancy with which value of ‘x’ is used while evaluating expression : (data == x + 1) ?
Assuming both sequences are true for ‘or’, ‘x’ would be assigned possibly different values at the same time.