In reply to dave_59:
Hi, I tried it with virtual if, but it still works on individual clocks. I suppose there is deep bug with my testbench. I post my code here:
`timescale 1ns / 1ps
import uvm_pkg::*;
`include "uvm_macros.svh"
interface type_rx_if(input bit clk);
wire done;
wire start;
clocking mck @(posedge clk);
inout done;
output start;
endclocking: mck
modport master(clocking mck);
endinterface
class test_case1 extends uvm_test;
`uvm_component_utils(test_case1)
virtual type_rx_if sigs[3:0];
function new(string name = "test_case1",
uvm_component parent=null);
super.new(name,parent);
endfunction : new
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
for (int i=0; i < 4; i=i+1) begin
if (!uvm_config_db#(virtual type_rx_if)::get(this, "", {"rx_vif_", i}, sigs[i])) begin
`uvm_fatal("DRV/NOVIF", "No virtual interface specified for this driver instance")
end
end
endfunction : build_phase
virtual protected task run_phase(uvm_phase phase);
phase.raise_objection(this, "running ");
super.run_phase(phase);
#200;
this.sigs[0].mck.start <= 1'b0;
this.sigs[3].mck.start <= 1'b0;
#200;
this.sigs[0].mck.start <= 1'b1;
this.sigs[3].mck.start <= 1'b1;
phase.drop_objection(this, " done");
endtask: run_phase
endclass : test_case1
module test_top ();
reg reset, clk, clk_sfp ;
type_rx_if rx_vif[3:0] ({clk_sfp,{3{clk}}});
genvar i;
generate
for (i=0; i < 4; i=i+1) begin
initial
begin
uvm_config_db#(virtual type_rx_if)::set(uvm_root::get(), "*", {"rx_vif_", i}, rx_vif[i]);
end
end
endgenerate
initial begin
run_test();
end
initial begin
clk <= 1'b0;
clk_sfp <= 1'b0;
#200;
rx_vif[3].mck.done <= 1'b0;
rx_vif[0].mck.done <= 1'b0;
#200;
rx_vif[3].mck.done <= 1'b1;
rx_vif[0].mck.done <= 1'b1;
end
always
#62.5 clk = ~clk;
always
#40 clk_sfp = ~clk_sfp;
endmodule
in my TB , I created 8 agents, I want to use 4 with clk1,4 with clk2, and instantiate the vif in the drv and mon as here in the test, but I can’t imagine what is the difference between my TB and this code. is it because of the 8 mons and drvs are array of the same class? or is there any other possible bug? anyhow, I think the interface related code only exist in drv, mon, interface definition and TB top, I did not use config to pass it down.