Assign random delay to existing clock

SystemVerilog
,
3

Hi Ben,

Thanks for you reply.
I think you misunderstood, I have one clock there named CLK, I want to delayed this clock by some random values. random delay should be from (0 to 1.28ns).

real rand_val;
initial begin
rand_val = $urandom_range(0,128)/100.0;
`uvm_info(“DELTA”, $sformatf(“Randomized delta: %f”, rand_val), UVM_NONE);
end

so here, I randomized the delay which is rand_val now I want my CLK to be delayed by that rand_val value. Is that you meant?