Assign delay behavioural differences

SystemVerilog
,
6

In reply to dave_59:

In reply to ceesam:
A continuous assignment to a reg variable should have been illegal in Verilog, so I assume that everything is being run in SystemVerilog.
Again, can you elaborate? What should the value be, and when should it change. Can you provide a small self-contained example that shows the difference you are seeing?

I would have thought illegal as well but it does not flag as an error/warning in the simulator (Cadence). Nothing in the LRM regarding this. I am simulation in SV.

module rtl ();

  reg       tmp1;
  reg       tmp2;
  wire      tmp3;
  wire      tmp4;
  
  assign #1 tmp1 = en;
  assign    tmp2 = en;
  assign #1 tmp3 = en;
  assign    tmp4 = en;

endmodule


module tb;

  rtl dut();

  initial begin

  dut.en=1;
  #5;
  dut.en=0;
  #4;
  dut.por=1;
  #1;
  
  end

endmodule