In reply to MayurKubavat:
In reply to ceesam:
Reg type is not a legal lvalue and cannot be used on left side of continuous assignments!(When used with .v file extension[Verilog]). However same piece of code will work when used with .sv file extension[SystemVerilog], in that case there’s no difference between both usage.
Changing the file extension to sv does not resolve the difference issue. If the left hand of the assignment is of type reg then the output is X.