Hi,
I want to make a variable size based on a design parameter.
for example,
if(condition) is met , size is 128 bits
bit [127:0] a;
else 256 bits
bit [255:0] a;
what is the best way to do this.
Thanks in advance.
Hi,
I want to make a variable size based on a design parameter.
for example,
if(condition) is met , size is 128 bits
bit [127:0] a;
else 256 bits
bit [255:0] a;
what is the best way to do this.
Thanks in advance.
In reply to theketi:
I recommend making the variable the largest you would need in every use mode and ignoring/bit-masking the unneeded bits.
In reply to theketi:
If condition is a parameter in the Verilog sense of that word, you can do:
bit [ (condition ? 128 : 255) : 0] a;
Hi
Some more questions on this topic.
The condition i have is not a parameter. Its not a constant. In fact its a random variable called size and the variables a,b are dependent on size.
So i have a dynamic array that i need to combine and assign to variable.
How can i assign according to size of dynamic array.
lets say ,
dyn_arr = new[2] {8’b1,8’b0};
bit[15:0] temp_var;
temp_var[15:0] = >>{dyn_arr};
but the dyn_arr size changes , how can i make it assigned to variable.
dyn_arr = new[size] {dyn_arr1};
temp_var[size-1:0] = >>{dyn_arr};
I dont want the temp_var size to be largest size as it has to be processed a lot later.
Thanks