In reply to ben@SystemVerilog.us:
Thanks Ben.
could you please let me know is there any practical scenario where constraint random tests failed to catch the bug,But Assertions will help to find that bug in design.
In reply to ben@SystemVerilog.us:
Thanks Ben.
could you please let me know is there any practical scenario where constraint random tests failed to catch the bug,But Assertions will help to find that bug in design.