Assertions

SystemVerilog
5

In reply to ben@SystemVerilog.us:

Thanks ben for the complete clarification.

if the property is a sequence then:

  1. req until gnt; == req[*1:]##1gnt;? or req until gnt == req[*0:] ##1gnt?
  2. req until_with gnt; == req[*1:]##0gnt;? or req until_with gnt; == req[*0:]##0gnt?

I am bit confused in using [*1:] and [*0:] please let me know

Thanks in advance