In reply to NIDHI MAKWANA:
Everything you wrote is correct, even the assertion.
Question: Why are you saying "However, this is not giving me the desired output."
You need to clarify what you are really looking for.
With your assertion, if the antecedent passes, then in the same cyle (since same clock) the assertion succeeds if ( $rose(a1) && $fell(b1) ) matches. Else, the consequent will wait for the nearest @(posedge clk2) and then check if ( $rose(a1) && $fell(b1) ) matches. If it does the assertion is true.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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