Error-[SVATHTLHS] Temporal LHS of ‘throughout’ operator.
A temporal LHS is not allowed with the ‘throughout’ operator.
Expression: (##1 ($stable(gray_count) || gray_count === “X”) throughout (iso_input[->0]))
Thank you for replying Ben. I tried your suggestion but still getting same error:
Error-[SVATHTLHS] Temporal LHS of ‘throughout’ operator.
A temporal LHS is not allowed with the ‘throughout’ operator.
Expression: (( ##1 ((stable(gray_count) || (gray_count == "X")) [* 1:]))
throughout (iso_input [-> 1]))
One doubt: why did you suggest to use throughout (iso_input[->1]) instead of throughout (iso_input[->0])?
Intention is to check validity of sequence until iso_input is de-asserted.
In reply to shivamdec:
My mistake on the troughout, see updated code below and sim results.
On [->0], that does not make sense.
b [->m] is equivalent to ( !b [*0:] ##1 b)[*m]
Thus, b[->0] is same as (!b[*0:] ##1 b)[*0] , and that is empty
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
bit clk, a, b, iso_input;
logic[4:0] start_addr, gray_count;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
ap_gray_cnt_value_chk: assert property(
@(posedge clk ) (start_addr == 'h10 && iso_input) |->
##1 ($stable(gray_count) || gray_count === "X") throughout (iso_input[->1]));
initial begin
repeat(200) begin
@(posedge clk);
if (!randomize(start_addr, iso_input, gray_count) with
{ start_addr dist {5'b10000:=3, 5'b01011:=1};
gray_count dist {3'b1:=101, 3'b111:=2};
iso_input dist {1'b0:=3, 1'b1:=1};
}) `uvm_error("MYERR", "This is a randomize error")
end
$stop;
end
endmodule
Thanks for explanation. But I am getting same error again :(
Error-[SVATHTLHS] Temporal LHS of ‘throughout’ operator.
A temporal LHS is not allowed with the ‘throughout’ operator.
Expression: (( ##1 ($stable(gray_count) || (gray_count === “X”))) throughout
(iso_input [-> 1]))
In reply to shivamdec:
******* PLEASE SEE MY CORRECTIONS BELOW THIS POST ********
I see the issue here.
1800’2012 says that a sequence is
expression_or_dist throughout sequence_expr
// and it is NOT the following
sequence throughout sequence_expr // ILLEGAL !!!!
What we have is
##1 ($stable(gray_count) || gray_count === "X") // a sequence
throughout (iso_input[->1]) // thus it is illegal
My tool is in error.
************** NOTE *************
[Ben] Errata: My tool is not in error, see my last post below
Actually, my original code was OK.
I was assuming that ##1 is associated with the LHS of throughout which is not correct. Note that there is no issue of operator precedence here as there is no ambiguity in how the above sequence expression should be parsed. The ## has higher precedence than the throughout.
The error code that you got from your vendor is your vendor’s error; it is not my vendor.
Ben Cohen http://www.systemverilog.us/ben@systemverilog.us
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