Assertions - Temporal LHS error in throughout operator

SystemVerilog
2

In reply to shivamdec:


property gray_cnt_value_chk;
        @(posedge clk ) (start_addr == 'h10 && iso_input) |-> 
##1 ($stable(gray_count) || gray_count === "X")[*1:$] throughout (iso_input[->1]);
    endproperty

You’re checking a sequence throughout another sequence
Ben systemverilog.us