In reply to ben@SystemVerilog.us:
I apologize for the confusion. I’ll pick up these concepts as suggested
My requirements:
At some point in time ‘sig_a’ transitions from 0->1 and stays there. Within say ‘x’ clock cycles, ‘sig_b’ should make a transition from 0->1 (all wrt clk and they initially start at ‘0’). In a similar fashion, bunch of other signals get triggered (more like a chain reaction).
I’m planning to write an assertion which fails if such transitions won’t occur according to the spec, otherwise they just move on. I would like to write them in a way that it just FAILS when things don’t happen according to the transition diagram.
Thanks a lot.