Assertions for Two clock cycles

SystemVerilog
,
4

In reply to ben@SystemVerilog.us:
If you want to add the error state test, then


bit error; 
// If error is clk1 drops for 2 or 3 half-cycles
// end the final test with 
... ##1 (1, f2(count)) ##0 (count==1 &&  error) ||  // drop for 3 half-cycles, error
                           (count==2 &&  error) ||  // drop for 2 half-cycles, error
                           (count==3 && !error) ||  // drop for 1 half-cycle, no error
                           (count==4 && !error);    // no drops