Assertions for Two clock cycles

SystemVerilog
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2

In reply to mpradhani:

Edit code - EDA Playground code
EPWave Waveform Viewer // waveform
This code has a lot of debug features; you’ll need to remove them for your needs.
The “go” was for debug to isolate the evaluation of the assertion to one attempt.


module top;
  bit clk10=1, clk1=0; 
  int pass, fail, start, thecount, im_fail;
  bit sp_clk1, go=1; // support logic 
  initial forever #3 clk10 = !clk10;
  initial forever #30 clk1 = !clk1;
  initial forever #30 sp_clk1 = !sp_clk1;
  
  function automatic void f(); start=start+1; go=0; endfunction // debug
  function automatic void f2(int v); thecount=v; endfunction // debug

  property p_clk1; 
    int count=0;
    bit vck1; 
    @(posedge sp_clk1) go |->  ##0 @(posedge clk10) ##1 (1, f()) ##0
                 ((1,count=count+1, vck1=clk1, f2(count)) ##5 
                  (1,count=count+ $changed(clk1), vck1=clk1, f2(count)) ##4 1)[*2] 
    ##1 (1, f2(count)) ##0 count==4;
   endproperty 
  ap_clk1: assert property(p_clk1) pass=pass+1; else fail=fail+1; 
    
    function automatic void f3(); im_fail=im_fail+1; endfunction
    // Does not meet the requirements for 2 cycles, but is presented as an idea. 
    am_clk1: assert final(clk1==sp_clk1) else f3(); 

  initial begin
    $dumpfile("dump.vcd"); $dumpvars;
    repeat(50) @(posedge clk10);
    $finish(2);
  end
    
   initial #100 force clk1=1; 
endmodule

Ben Cohen
Ben@systemverilog.us
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