Assertion variable delay

SystemVerilog
1

Hi,

I need to write an assertion that wait at least X ns between rose(a) and rose(b).
X is a variable that come as argument.
it is illegal to write $rose(a) ##[x:$] |-> $rose(b)
I tried this code:

sequence delay_seq(v_delay);
         int delay;
        (1,delay=v_delay) ##0 first_match((1,delay=delay-1) [*0:$] ##0 delay <=0);
endsequence

    aasert_Ts_1 : assert property (@(posedge assert_clk) $rose(a)) |-> delay_seq(10) |-> $rose(b));

but it’s not work ok.
how can I resolve this issue?

Thanks

2

Please format your code making your code easier for others to read. I have done that for you.

You would do the same way as shown here, except that a and b become your two clocks.

3

Thanks @dave_59 .
it seems that the example you gave me, is how to implement clock period checker, not?
I look for how to implement

|-> ##[10:$]

10 value should be variable.

Thanks.

4

I guess (1,delay=delay-1) [*0:$] ##0 delay <= 0 should be (1,delay=delay-1) [*0:$] ##1 delay <= 0.

Please refer to the following. I believe they are helpful to you.

sva_repeat_delay_thru_pkg_011624.sv

sva_repeat_delay_thru_pkg_011624.pdf (89.0 KB)

5

Thanks @Orimitsu

It works to me.

I’ll be happy if you can explain the code, in order to understand what more I can check with it.

Thank a lot.

6

Hi @Brurya ,

[*1:$] ##1 delay <= 0 is non overlapping while [*1:$] delay ##0 delay <= 0 is overlapping.
That is, delay value is evaluated after count down in non overlapping. On the other hand, delay is evaluated at the same cycle of count down.

[1:$] ##0 delay <= 0
         |  Count Down Sequence    |
         |              -1 -1 -1 -1|
 delay : | v_delay ...   3  2  1  0
            ......................*|
                        Overlap ->| delay <= 0 ?

[1:$] ##1 delay <= 0
         |  Count Down Sequence |
         |              -1 -1 -1|
 delay : | v_delay ...   3  2  1  0
            ......................*|
                    Non Overlap ->| definetely delay <= 0

I guess the value of delay at the evaluation cycle is not deterministic in case of overlapping.

7

Thank a lot @Orimitsu

8

Why do we need to specify ##1 delay <= 0 ? Shouldn’t it be ##1 delay == 0?

9

Hi @dvfunda,

To avoid delay value decrement and its evaluation at the same clock cycle. The value of delay is definitive in the next clock cycle.

10

Hi @Orimitsu ,

Thanks for the reply. My doubt was regarding delay <= 0. I believe, delay will be 0 at the last cycle.

11

Hi @dvfunda,

Oh, I see. delay == 0 also works. I guess delay <= 0 is only for just in case. Ben Cohen’s sample sequences is in such a style.
I think a lot of people is referring to them.

12

Hmm, Thanks @Orimitsu for the clarification.