Assertion using $stable with |-> #[...]

SystemVerilog
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In reply to ingamara:
Your code will be checked as below.

assert property(@(posedge clock) $rose(A) |-> ##[1:2] $stable(B));

Once $rose(A) is true $stable(B) can be true either in the first or second cycle after $rose(A) is true.

You can write the code as below using continuous repetition operator[*n]. Using this operator $stable(B) will be checked for true condition continuously for two cycles after $rose(A) is true.


 property p1;
    @(posedge clk) $rose(A)|=> $stable(B)[*2];
endproperty
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