In reply to bhajanpreetsinght:
In reply to ben@SystemVerilog.us:
( req you elaborate on this why we use B||c = don’t care ,we care it should be high we are checking till the period is A is high and stop if A goes low and B and C is high.
Hi Ben,
Thanks for the reply but we need to keep on checking value of B || c to be high throughout A is high and stop if only A goes low and they donot get the value of B || c to be high. Can you comment on this
so basically assertion fails if a is high and we donot get either b or c is high in the time period of A is high and if we get either of them to be high in the time period of a is high the assertion passes .